CLK Q0 Q1 Q2 Q0 is delayed by 1 propagation delay, Q2 by 2 delays and Q3 by 3 delays. Notice how delays are cumulative as each stage in a counter is clocked later than the previous stage. For certain applications requiring high clock rates, this is a major disadvantage. Summary Propagation Delay Asynchronous counters are sometimes called ripple counters, because the stages do not all change together. The resulting sequence is that of an 3-bit binary up counter. The leading edge of Q0 is equivalent to the trailing edge of Q0. The following stage is triggered from Q0. Summary Three bit Asynchronous Counter Notice that the Q0 output is triggered on the leading edge of the clock signal. It uses J-K flip-flops in the toggle mode. The three-bit asynchronous counter shown is typical. Subsequent stages derive the clock from the previous stage. HIGH Q0 Q1 Q2 J0 J1 J2 CLK C C C Q0 Q1 K0 K1 K2 Summary Three bit Asynchronous Counter In an asynchronous counter, the clock is applied only to the first stage. The first stage in the counter represents the least significant bit – notice that these waveforms follow the same pattern as counting in binary. Summary Counting in Binary A counter can form the same pattern of 0’s and 1’s with logic levels. The next bit changes on every fourth number.
The next bit changes on every other number. Summary Counting in Binary As you know, the binary count sequence follows a familiar pattern of 0’s and 1’s as described in Section 2-2 of the text. Digital Fundamentals Tenth Edition Floyd Chapter 8 © 2008 Pearson Education
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